NULL Convention LogicTM
Summary:
Theseus Logic, Inc., with the help of BMDO SBIR funding, has developed an asynchronous logic expected to have a broad impact on the semiconductor industry. Called NULL Convention LogicTM (NCL), this patented technology offers considerable performance advantages over the clock-driven Boolean logic used in digital electronic circuits today. Theseus formed a strategic alliance with Motorola's Semiconductor Products Sector to jointly implement clockless versions of Motorola’s 32-bit M?CORE processor and its newest 8-bit microcontroller.
Technology Description:
Theseus Logic, Inc., has developed and patented NULL Convention LogicTM (NCL), an asynchronous logic expected to have a broad impact on the microprocessor industry. NCL makes possible a new design paradigm for digital electronics, wherein the clock function of conventional integrated circuits (ICs) is eliminated entirely.
NCL is inherently different from the conventional Boolean logic used in nearly all integrated circuits today. Traditional Boolean logic is based on two mutually exclusive values—true(1) and false (0). Unfortunately, the Boolean logic circuit itself cannot decide when to receive or release data, therefore a clock must be added to control input and output. In contrast, the clockless NCL is data-driven: instructions are acted upon the moment they are available, and the output is available the moment it is completed. Employing discrete threshold gates that recognize only certain simultaneous combinations of values, the NCL design generates one additional state that is used for input/out control. This is called the NULL state, a non-data value used to reset the logic gates in the circuit. Each logic gate acts as a “synchronization node,” making the circuit, as a whole, symbolically complete. This means the circuit itself needs no external control devices.
Clockless, asynchronous circuits have been pursued by the microelectronics industry since the 1950s, and the potential benefits have been widely appreciated. As demands for chip performance increase, and each new generation of chip is more complex than the previous, their clocking schemes become increasingly problematic. Clocks consume significant portions of design and manufacturing budgets, hamper increased complexity and speed, and limit new portable applications due to power consumption. Therefore, some form of asynchronous logic may well become a design necessity in the next few years.
Many large microelectronic corporations have asynchronous research efforts underway. However, much of their work is geared to fitting Boolean logic to an asynchronous methodology, leading to extra circuitry and design complexity. NCL is built on standard complementary metal oxide semiconductors (CMOS), and requires no additional masking levels or additional circuitry
which raise production costs. Space requirements are likewise competitive. Theseus has had 19 patents issued for its technology, with one more patent allowed, and 20 patents pending.
With NCL design, circuits of arbitrary complexity can be designed by simply connecting smaller modules together, without any consideration of timing issues other than system throughput requirements. Once a circuit module is designed in NCL, it can be put into a library and reused in new applications and in new fabrication processes forever. NCL’s design reuse and process portability attributes are critical for redesigning existing chips or designing new chips for lower cost.
Up to 50 percent of the design costs and 25 percent of the manufacturing costs may be required to implement clock circuitry. Asynchronous design eliminates the timing issues that can be a headache for software developers. The asynchronous demand-driven processing saves power, as only those logic gates processing data consume power. In addition, NCL chips can easily be inserted into clocked Boolean system architectures, enabling electronic system designers to gracefully introduce this new technology on a chip-by-chip basis, without the need to redesign entire product architectures.
MDA Origins:
BMDO is interested in applying asynchronous circuits to high-speed computers. Theseus received a Phase I SBIR contract to support development of NCL implementation approaches, and completed a $750,000 BMDO Phase II SBIR contract, part of which was dedicated to develop nine functional NCL prototype chips. These chips contain up to 170,000 transistors. BMDO has also awarded a second Phase I SBIR award to Theseus to investigate asynchronous processor architectures.
Spinoff Applications:
Spinoffs from NCL could greatly influence the entire field of computing and digital technology. Some features of NCL asynchronous circuits include: ease and evolution of design, potentially superior performance characteristics, improved reliability and efficiency, and the ability to take advantage of ever-shrinking fabrication technologies.
NCL could enable the creation of entirely new classes of chips as well as systems-level products. Its initial impact is expected to be in low EMI, low power niches. Eventually, the benefits of NCL are expected to have a profound effect on the emerging portable digital electronics market.
If NCL proves competitive, it could have a major impact on the semiconductor industry, which is predicted to reach $300 billion by 2004. It could enable the creation of whole new classes of microprocessors and other integrated circuits (ICs) that are cheaper, smaller, faster, and more energy efficient.
Theseus has demonstrated commercially valuable aspects of its chip technology, including lower power consumption (only gates that are processing data actually consume power) and true breadboarding capability.
Commercialization:
Theseus’ business strategy is to aggressively protect its intellectual property, develop strategic alliances with established corporations, and create a licensing company capable of working with system developers to bring competitive asynchronous chips to market. Long term goals include broadly licensing the technology to semiconductor manufacturers and to provide design tools.
In November 1999, Theseus formed a strategic alliance with Motorola's Semiconductor Products Sector to implement NCL versions of Motorola's 32-bit MCORE processor and its newest 8-bit microcontroller. MCORE processors will be used in a wide variety of embedded applications. The Motorola MCore Web site reads: “The MCORE microRISC core introduces a new level of performance for embedded applications—a low-power architecture designed to bring unprecedented performance to a whole new class of applications.” The site lists applications ranging from digital phones, personal digital assistants and GPS receivers, to automotive products like braking systems and engine control.
Michael Graff was hired as president and CEO. Graff has 34 years experience in the semiconductor and communications industry. Prior to joining Theseus, Graff was vice president of Strategy and Business Development at Harris Semiconductor.
Company Profile:
Theseus began operations in January 1996 and now is headquartered in Orlando, FL. The company also opened a “Silicon Valley” office in Santa Clara, CA. The company aims to become a major supplier of intellectual property and system-on-a-chip solutions to electronics OEM's, and ultimately, to create the next design paradigm for the semiconductor industry by licensing NCL as an enabling technology broadly throughout the semiconductor industry.
Contact Information:
Mr. Ken Wagner, EVP Business Development
Theseus Logic, Inc.
3501 Quadrangle Blvd Suite 100
Orlando FL 32817
Tel:407-380-9008
Fax:407-380-9509
Cell Phone: 407-342-0673
email: kwagner@theseus.com
*UPDATE: Theseus merged with Camgian Microsystems
web: www.camgian.com
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