Summary:

A BMDO SBIR Phase I contract for virtual memory redundancy management
has led to an error-correction code (ECC) for data transmission systems that are more efficient than current methods in use. ECCs are used in all forms of digital circuitry and communications, from CD players to satellite links. The ECC was originally developed by GORCA Systems Incorporated (GSI; Cherry Hill, NJ) and then used as the basis for the formation of GORCA Memory Systems, Inc. (GMS; Cherry Hill, NJ). In 1999 that version of the ECC was purchased by Science Dynamics Corporation (SIDY; Cherry Hill, NJ). The ECC has since been enhanced by a combination of engineering efforts from SIDY and Technology Enhancement Partners, LLC (TEP; Medford, NJ). The first product of this joint effort is to be packaged in an error-correction chip for use in wireless local area networks and marketed by SIDY. Additional products are being developed by SIDY and TEP together and separately.

Technology Description:

In the mid 1990s, GORCA Memory Systems (GMS; Cherry Hill, NJ) was formed to create and market products using an error-correction code (ECC) that was developed by Walter Helbig, a consultant to GORCA Systems Incorporated (GSI; Cherry Hill, NJ). The system was purchased by Science Dynamics Corporation (SIDY; Cherry Hill, NJ) when GMS went out of business. SIDY and Technology Enhancement Partners, LLC (TEP; Cherry Hill, NJ) are jointly refining the ECC and developing new products and applications using it.

Error correcting is essential for error-free transmission of digital data. Whenever one digital component is tasked with sending bits to a second component (a “component” may be any digital device such as a cellular phone, computer network card, or computer memory that transmits data to the computer's processor), the possibility for the data set becoming corrupted in route arises. Error correction is made available by adding checksum bits to the packets of data that move between components. These bits allow the receiving component to determine if the packet of data arrived intact. Unfortunately, checksum bits also add overhead to each data packet (“overhead” is the percentage of checksum bits to data bits per packet). The larger the overhead, the lengthier the packets, and, therefore, the longer it takes for the entire set of data to be transmitted.

GMS's patented ECC is a form of a computable rotational code that can operate as a single burst-error correcting, multiple burst-error detecting code. Whereas most industry standard schemes, such as the Reed-Solomon (RS) code, operate at a fixed symbol length and, in typical implementations require an overhead of approximately eight percent, this code is designed to operate in the same applications with a much smaller overhead, typically on the order of one percent. The arithmetic process used with this code is similar to that used in the National Security Agency's secure hash algorithm (SHA-1). As such, the computational rate is much higher than it is for the RS code while the cost of implementation is anticipated to be considerably less. Further, the code provides modification correction capability in addition to modification detection capability at costs approximately equal to that of the SHA-1 code. Because there are virtually an infinite number of variations to this code, users can implement the single version or multiple versions that optimally match the intended application.

This ECC can facilitate further efficiency in virtual memory-addressing settings, because part of the ECC can be implemented on the virtual memory translation unit itself. Plus, because of its compact design, this code can be implemented on a single field-programmable gate array, which is a type of programmable logic chip, thereby saving production costs over error-correcting schemes that require more elaborate hardware.

MDA Origins:

In 1992, GSI completed a BMDO SBIR Phase I on virtual memory redundancy management for reliable multiprocessing. BMDO needed to facilitate complex, low-error rate data communications between satellite and ground systems. The original design was for a block-error correction for high-capacity, high-performance, solid-state memory systems.

Spinoff Applications:

Although error corrections are used in all forms of digital circuitry, from CD players to computers, efficient error correction is particularly valued in wireless communications, where throughput is already more limited than land-based lines. So everything from satellite communication links to cell phones could benefit from efficient error correction.

One possible application is in wireless local area networks (WLANs). These are similar to office networks of computers but, instead of the computers being attached to one another by cables, they communicate by radio signals. WLANS are useful for companies in old buildings where cable installation is costly or prohibitive. They might also be used with offices that are mobile. According to the Cahners In-Stat Group research firm, the corporate WLAN market may be worth $2.2 billion by 2004.

Another application area is in digital signatures. A digital signature is code that identifies the sender of an electronic document. Digital signatures were created to provide the electronic equivalent to written signatures. That is to say, they can guarantee the identity of the signer of the document. Because of this, digital signatures are predicted to become a cornerstone of the e-commerce marketplace, which requires authentication to conduct business. This ECC can be used in a digital signature system and can provide an additional benefit of error-correcting documents as they are transmitted.

Commercialization:

The present version of the error-detecting and correcting system is now jointly owned by SIDY and TEP. The first product that employs the technology is a forward error-correcting (FEC) chip that SIDY is now marketing. GMS’ principal investigator Walter Helbig, who founded TEP, is making further improvements to the ECC for applications for both companies.

SIDY and TEP have designed the forward error correcting (FEC) chip using this technology, called HSBC (Helbig-Shrinivasan Block Code) Burst Error Detection and Correction (HEDCtm). This chip could be used in commercial satellite terminals to replace the larger, more expensive, and less efficient Reed-Solomon FEC (which has about an eight-percent communication overhead).

TE is proposing that the HEDC chip (or variants of it) be accepted by the IEEE 802 standards bodies for the newer communications systems. The value of this code and its implementation can be seen in that in a typical WLAN one in every 100,000 packets transmitted will be received with errors. SIDY and TEP have shown that HEDC can, in this application, correct all these errors. Plus, they have shown that the HEDC chip is less costly than the Reed-Solomon components for the same system, as its efficient design can be implemented entirely on one integrated circuit. SIDY estimates that its HEDC chip will cost approximately a tenth of the full set of components for the Reed-Solomon unit. The HEDC FEC chip can work either in half-duplex or full-duplex mode, and has a capability of over 20 megabits per second, with gigabyte-level throughput possible. Further, the HEDC chip can automatically switch between handling short command packets (of up to 512 data bytes in length) and longer information packets (of over 512 data bytes in length).

SIDY may also employ the ECC in the global telecommunications network being built by SIDY for Cascadent Communications, Ltd. (Washington, D.C.). SIDY is a supplier of key technologies to this company, which has an ambitious plan for building a seamless Internet protocol-based global communications facility for large to medium corporate users with international communications requirements.

TEP is working toward employing the ECC as a part of secure computer systems. It is working with the McLean, VA-based Amron Corporation on an SBIR Phase I contract for the Navy SPAWAR program. The work involves the creation of a Security Level B-2 computer design. The company is also working on ways to implement the ECC into the efforts of the Trusted Computing Platform Alliance (http://www.trustedpc.org), a coalition of computer vendors interested in embedding stronger security functionality within computers. In these applications, the ECC can be implemented in the system's basic input/output system (BIOS) setting to insure that documents that are called up on a computer haven't been tampered with since the last authorized use. The ECC can also restore corrupted documents to their former state.

Company Profile:

GORCA Memory Systems went out of business in 1999. The intellectual property of the error correcting system was sold to SIDY. SIDY, incorporated in 1973, specializes in telecommunications systems, including intelligent call processing platforms which provide telecommunications service capabilities to the public switched telephone network. The company has recently focused on providing products for packet-based data networks. TEP has spearheaded the development of refinements to the ECC to add capabilities not available with other ECCs. TEP, working jointly with SIDY, has led the development of HEDC FEC chip which SIDY will produce and market.

Contact Information:

Walter Helbig(original principal investigator at GORCA Systems, Inc. for the BMDO SBIR Phase I project)
Technology Enhancement Partners, LLC
51 Haddonfield Road Suite 340
Cherry Hill NJ 08002-4810
Tel:609-654-6865
Fax:Same
email: walter_helbig@email.msn.com

Fred Miller
Science Dynamics Corporation
1919 Springdale Road
Cherry Hill NJ 08003
Tel:856-424-0068 x604
Fax:856-751-7361
email: sales@scidyn.com
web: http://www.scidyn.com/